The field of the invention relates to trenches formed in a substrate, and more particularly to trench memory devices having a vertical transistor above a trench capacitor.
FIG. 8B illustrates in simplified form a cross section of a pair of DRAM cells formed in substrate 10 and having a P-well 15. A trench has been etched into the substrate and capacitor 100 has been formed in the lower portion, with dielectric 107 and center electrode 110. In the upper portion of the trench, a vertical transistor 200 has been formed, with buried strap 127 as the lower electrode.
In the course of etching a deep trench in a silicon substrate, a conventional configuration of orienting the trench in the substrate is the <100> configuration, in which the long axis of the oval trenches are printed at the wafer surface are parallel to a <100> crystallographic direction of the substrate (diagramed in FIG. 8A). In this configuration, the formed trench assumes a square shape in the bottom, as shown in FIG. 9A; an oval shape at wafer surface, as shown in FIG. 9C; and an octagon shape in the upper portion of the trench, as shown in FIG. 9B. The change of trench shape at different depth is due to the fact that etch rates are different at different crystallographic orientations. Specifically, the {100} surfaces of the silicon are etched at a greater rate than the {110} surfaces.
The <100> configuration is conventionally chosen because the differential etching along the crystal planes produces a square cross section that packs together tightly, even after the step of bottle etching, so that the capacitance can be maximized by using the bottle etch step, without having an excessive risk of trench merging. However, the octagonal cross section of the upper trench where the vertical transistor is formed matches poorly with the stripe that defines the active area (AA) by defining the isolation structures that separate devices and structures on the wafer surface.
FIG. 9B shows AA strips 910 that meet the octagons 920 that represent the trench cross section such that the corners of the octagons are at the trench-AA intersection. This results in the undesired variation of vertical transistor characteristics such as threshold voltage (Vt) when the trench-AA intersection is located slightly away from the corner or at the corner of the octagon.
Thus, the requirement of getting the highest capacitance in the trench and avoiding shorts between capacitors conflicts with the need for a tight alignment tolerance between the trench and the AA level.
The art could benefit from a trench capacitor—vertical transistor process that preserves tight tolerance between the trench and the active area.